Atmel C51 Fiche technique

Rev. 4180E–8051–10/06Features• 80C52 Compatible– 8051 Pin and Instruction Compatible– Four 8-bit I/O Ports – Three 16-bit Timer/Counters– 256 Bytes Sc

10AT89C51RB2/RC24180E–8051–10/06 Table 12. Pin Description for 40 - 44 Pin Packages MnemonicPin NumberType Name and FunctionDIL LCC VQFP44 1.4VSS20 2

100AT89C51RB2/RC24180E–8051–10/06ExampleHOST : 01 0010 00 55 9ABOOTLOADER : 01 0010 00 55 9A . CR LFProgramming Data (write 55h at address 0010h in t

101AT89C51RB2/RC24180E–8051–10/06Blank Check CommandDescriptionFigure 43. Blank Check FlowExampleHostBootloaderBlank Check Command ’X’ & CR &

102AT89C51RB2/RC24180E–8051–10/06Display DataDescriptionFigure 44. Display FlowNote: The maximum size of block is 400h. To read more than 400h Bytes,

103AT89C51RB2/RC24180E–8051–10/06ExampleRead Function This flow is similar for the following frames:• Reading Frame• EOF Frame/Atmel Frame (only readi

104AT89C51RB2/RC24180E–8051–10/06ISP Commands Summary Table 73. ISP Commands Summary Command Command Name Data[0] Data[1] Command Effect00h Program D

105AT89C51RB2/RC24180E–8051–10/06API Call Description Several Application Program Interface (API) calls are available for use by an applicationprogram

106AT89C51RB2/RC24180E–8051–10/06PROGRAM X2 FUSE 0AhFuse value00h or 01h0008h XXh none Program X2 fuse bit with ACCPROGRAM BLJB FUSE0AhFuse value00h o

107AT89C51RB2/RC24180E–8051–10/06Electrical CharacteristicsAbsolute Maximum RatingsDC Parameters for Standard VoltageC = commercial...

108AT89C51RB2/RC24180E–8051–10/06Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Fig

109AT89C51RB2/RC24180E–8051–10/06DC Parameters for Low VoltageTA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0to 40 MHzTA = -40°C to +85°C; VSS

11AT89C51RB2/RC24180E–8051–10/06I/O CEX4: Capture/Compare External I/O for PCA Module 4P1.0 - P1.7 I/O MOSI: SPI Master Output Slave Input lineWhen

110AT89C51RB2/RC24180E–8051–10/06If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current

111AT89C51RB2/RC24180E–8051–10/06AC ParametersExplanation of the AC SymbolsEach timing symbol has 5 characters. The first character is always a “T” (s

112AT89C51RB2/RC24180E–8051–10/06Table 76. AC Parameters for a Fix ClockTable 77. AC Parameters for a Variable ClockSymbol -M -L UnitsMin Max Min Ma

113AT89C51RB2/RC24180E–8051–10/06External Program Memory Read CycleExternal Data Memory Characteristics Table 78. Symbol DescriptionTPLIVTPLAZALEPSEN

114AT89C51RB2/RC24180E–8051–10/06Table 79. AC Parameters for a Fix ClockSymbol-M -LUnitsMin Max Min MaxTRLRH125 125 nsTWLWH125 125 nsTRLDV95 95 nsTRH

115AT89C51RB2/RC24180E–8051–10/06External Data Memory Write CycleSymbol TypeStandard Clock X2 ClockX Parameter for -M RangeX Parameter for -L Range Un

116AT89C51RB2/RC24180E–8051–10/06External Data Memory Read CycleSerial Port Timing - Shift Register ModeTable 80. Symbol DescriptionTable 81. AC Par

117AT89C51RB2/RC24180E–8051–10/06Shift Register Timing WaveformsExternal Clock Drive WaveformsAC Testing Input/Output WaveformsAC inputs during testin

118AT89C51RB2/RC24180E–8051–10/06Figure 50. Internal Clock SignalsThis diagram indicates when signals are clocked internally. The time it takes the s

119AT89C51RB2/RC24180E–8051–10/06Ordering InformationTable 83. Possible Order EntriesPart Number Memory Size Supply Voltage Temperature Range Package

12AT89C51RB2/RC24180E–8051–10/06PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program memory. When executing code from the exter

120AT89C51RB2/RC24180E–8051–10/06Package InformationPDIL40

121AT89C51RB2/RC24180E–8051–10/06VQFP44

122AT89C51RB2/RC24180E–8051–10/06PLC44

123AT89C51RB2/RC24180E–8051–10/06Datasheet Change LogChanges from 4180A-08/02 to 4180B-04/031. Changed the endurance of Flash to 100, 000 Write/Erase

Table of ContentsiTable of ContentsFeatures ... 1Descrip

iixxxxA–8051–10/06Registers... 47Baud Rate S

iiixxxxA–8051–10/06DC Parameters for Standard Voltage... 107DC Parameters for Low Voltage.

Printed on recycled paper.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied,

13AT89C51RB2/RC24180E–8051–10/06Port Types AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output thatis common on the 80C51 a

14AT89C51RB2/RC24180E–8051–10/06Oscillator To optimize the power consumption and execution time needed for a specific task, aninternal, prescaler feat

15AT89C51RB2/RC24180E–8051–10/06Functional Block DiagramFigure 4. Functional Oscillator Block DiagramPrescaler Divider • A hardware RESET puts the pr

16AT89C51RB2/RC24180E–8051–10/06Enhanced Features In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new fea-tures, which are:• X

17AT89C51RB2/RC24180E–8051–10/06Figure 6. Mode Switching WaveformsThe X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock peri

18AT89C51RB2/RC24180E–8051–10/06Table 15. CKCON0 RegisterCKCON0 - Clock Control Register (8Fh)Reset Value = 0000 000’HSB. X2’b (see Table 65 “Hardwar

19AT89C51RB2/RC24180E–8051–10/06Table 16. CKCON1 RegisterCKCON1 - Clock Control Register (AFh)Reset Value = XXXX XXX0bNot bit addressable76543210----

2AT89C51RB2/RC24180E–8051–10/06The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internalRAM, a 9-source 4-level interrupt contro

20AT89C51RB2/RC24180E–8051–10/06Dual Data Pointer Register (DPTR)The additional data pointer can be used to speed up code execution and reduce codesiz

21AT89C51RB2/RC24180E–8051–10/06Table 17. AUXR1 registerAUXR1- Auxiliary Register 1(0A2h)Reset Value = XXXX XX0X0bNot bit addressableNote: 1. Bit 2

22AT89C51RB2/RC24180E–8051–10/06INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in theAUXR1 SFR. However, note that the IN

23AT89C51RB2/RC24180E–8051–10/06Expanded RAM (XRAM)The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM)space for increased data

24AT89C51RB2/RC24180E–8051–10/06• Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data wher

25AT89C51RB2/RC24180E–8051–10/06Registers Table 19. AUXR RegisterAUXR - Auxiliary Register (8Eh)Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65)Not

26AT89C51RB2/RC24180E–8051–10/06Timer 2 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is mai

27AT89C51RB2/RC24180E–8051–10/06Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1)Programmable Clock-out ModeIn the clock-out mode, Timer 2 oper

28AT89C51RB2/RC24180E–8051–10/06Figure 10. Clock-Out Mode C/T2 = 0:6EXF2TR2OVER-FLOWT2EXTH2(8-bit)TL2(8-bit)TIMER 2RCAP2H(8-bit)RCAP2L(8-bit)T2OET2FC

29AT89C51RB2/RC24180E–8051–10/06Registers Table 20. T2CON RegisterT2CON – Timer 2 Control Register (C8h)Reset Value = 0000 0000bBit addressable765432

3AT89C51RB2/RC24180E–8051–10/06Block DiagramFigure 1. Block DiagramNotes: 1. Alternate function of Port 1.2. Alternate function of Port 3.Timer 0INTR

30AT89C51RB2/RC24180E–8051–10/06Table 21. T2MOD RegisterT2MOD – Timer 2 Mode Control Register (C9h)Reset Value = XXXX XX00bNot bit addressable7654321

31AT89C51RB2/RC24180E–8051–10/06Programmable Counter Array (PCA)The PCA provides more timing capabilities with less CPU intervention than the standard

32AT89C51RB2/RC24180E–8051–10/06Figure 11. PCA Timer/CounterCIDL CPS1 CPS0 ECFItCH CL16-bit up CounterTo PCAModulesFCLK PERIPH/6FCLK PERIPH/2T0 OVFP1

33AT89C51RB2/RC24180E–8051–10/06Registers Table 22. CMOD RegisterCMOD – PCA Counter Mode Register (D9h)Reset Value = 00XX X000bNot bit addressableThe

34AT89C51RB2/RC24180E–8051–10/06Table 23. CCON RegisterCCON – PCA Counter Control Register (D8h)Reset Value = 000X 0000bBit addressableThe watchdog t

35AT89C51RB2/RC24180E–8051–10/06Figure 12. PCA Interrupt SystemPCA Modules: each one of the five compare/capture Modules has six possible func-tions

36AT89C51RB2/RC24180E–8051–10/06Table 24. CCAPMn Registers (n = 0-4)CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh)CCAPM1 – PCA Module

37AT89C51RB2/RC24180E–8051–10/06Table 25. PCA Module Modes (CCAPMn Registers)There are two additional registers associated with each of the PCA Modul

38AT89C51RB2/RC24180E–8051–10/06Table 27. CCAPnL Registers (n = 0-4)CCAP0L – PCA Module 0 Compare/Capture Control Register Low (0EAh)CCAP1L – PCA Mod

39AT89C51RB2/RC24180E–8051–10/06PCA Capture Mode To use one of the PCA Modules in the capture mode either one or both of the CCAPMbits CAPN and CAPP f

4AT89C51RB2/RC24180E–8051–10/06SFR Mapping The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the followingcategories:• C51 core re

40AT89C51RB2/RC24180E–8051–10/0616-bit Software Timer/ Compare ModeThe PCA Modules can be used as software timers by setting both the ECOM and MATbits

41AT89C51RB2/RC24180E–8051–10/06High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggleeach time a m

42AT89C51RB2/RC24180E–8051–10/06Pulse Width Modulator ModeAll of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM func-tion. The fr

43AT89C51RB2/RC24180E–8051–10/06changing the time base for other Modules would not be a good idea. Thus, in most appli-cations the first solution is t

44AT89C51RB2/RC24180E–8051–10/06Serial I/O Port The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the80C52.It provid

45AT89C51RB2/RC24180E–8051–10/06Figure 19. UART Timings in Modes 2 and 3 Automatic Address RecognitionThe automatic address recognition feature is en

46AT89C51RB2/RC24180E–8051–10/06The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-car

47AT89C51RB2/RC24180E–8051–10/06Registers Table 30. SADEN RegisterSADEN - Slave Address Mask Register (B9h)Reset Value = 0000 0000bNot bit addressabl

48AT89C51RB2/RC24180E–8051–10/06Table 32. Baud Rate Selection Table UARTInternal Baud Rate Generator (BRG)When the internal Baud Rate Generator is us

49AT89C51RB2/RC24180E–8051–10/06Table 33. SCON RegisterSCON - Serial Control Register (98h)Reset Value = 0000 0000bBit addressable76543210FE/SM0 SM1

5AT89C51RB2/RC24180E–8051–10/06Table 2. C51 Core SFRsMnemonicAddName 76543210ACC E0h AccumulatorB F0h B RegisterPSW D0h Program Status Word CY AC F0

50AT89C51RB2/RC24180E–8051–10/06Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1Table 35. Example of Computed Value When X2=0, SMOD1=0,

51AT89C51RB2/RC24180E–8051–10/06Table 38. SBUF RegisterSBUF - Serial Buffer Register for UART (99h)Reset Value = XXXX XXXXbTable 39. BRL RegisterBRL

52AT89C51RB2/RC24180E–8051–10/06Table 40. T2CON RegisterT2CON - Timer 2 Control Register (C8h)Reset Value = 0000 0000bBit addressable76543210TF2 EXF2

53AT89C51RB2/RC24180E–8051–10/06Table 41. PCON RegisterPCON - Power Control Register (87h)Reset Value = 00X1 0000bNot bit addressablePower-off flag r

54AT89C51RB2/RC24180E–8051–10/06Table 42. BDRCON RegisterBDRCON - Baud Rate Control Register (9Bh)Reset Value = XXX0 0000bNot bit addressablef7654321

55AT89C51RB2/RC24180E–8051–10/06Interrupt System The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0and INT1), three

56AT89C51RB2/RC24180E–8051–10/06Registers A low-priority interrupt can be interrupted by a high-priority interrupt, but not by anotherlow-priority int

57AT89C51RB2/RC24180E–8051–10/06Table 44. IENO RegisterIEN0 - Interrupt Enable Register (A8h)Reset Value = 0000 0000bBit addressable76543210EA EC ET2

58AT89C51RB2/RC24180E–8051–10/06Table 45. IPL0 RegisterIPL0 - Interrupt Priority Register (B8h)Reset Value = X000 0000bBit addressable76543210- PPCL

59AT89C51RB2/RC24180E–8051–10/06Table 46. IPH0 RegisterIPH0 - Interrupt Priority High Register (B7h)Reset Value = X000 0000bNot bit addressable765432

6AT89C51RB2/RC24180E–8051–10/06Table 6. Timer SFRsMnemonicAddName 76543210TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0TMOD

60AT89C51RB2/RC24180E–8051–10/06Table 47. IEN1 RegisterIEN1 - Interrupt Enable Register (B1h)Reset Value = XXXX X000bBit addressable76543210-----ESPI

61AT89C51RB2/RC24180E–8051–10/06Table 48. IPL1 RegisterIPL1 - Interrupt Priority Register (B2h)Reset Value = XXXX X000bBit addressable76543210- - - -

62AT89C51RB2/RC24180E–8051–10/06Table 49. IPH1 RegisterIPH1 - Interrupt Priority High Register (B3h)Reset Value = XXXX X000bNot bit addressable765432

63AT89C51RB2/RC24180E–8051–10/06Interrupt Sources and Vector AddressesTable 50. Interrupt Sources and Vector AddressesNumber Polling Priority Interru

64AT89C51RB2/RC24180E–8051–10/06Keyboard Interface The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboa

65AT89C51RB2/RC24180E–8051–10/06Registers Table 51. KBF RegisterKBF - Keyboard Flag Register (9Eh)Reset Value = 0000 0000bThis register is read only

66AT89C51RB2/RC24180E–8051–10/06Table 52. KBE RegisterKBE - Keyboard Input Enable Register (9Dh)Reset Value = 0000 0000b76543210KBE7 KBE6 KBE5 KBE4 K

67AT89C51RB2/RC24180E–8051–10/06Table 53. KBLS RegisterKBLS - Keyboard Level Selector Register (9Ch)Reset Value = 0000 0000b76543210KBLS7 KBLS6 KBLS5

68AT89C51RB2/RC24180E–8051–10/06Serial Port Interface (SPI)The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serialcommuni

69AT89C51RB2/RC24180E–8051–10/06drive the network. The Master may select each Slave device by software through portpins (Figure 26). To prevent bus co

7AT89C51RB2/RC24180E–8051–10/06Table 8. Serial I/O Port SFRsMnemonicAddName 76543210SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RISBUF 99h

70AT89C51RB2/RC24180E–8051–10/06Functional Description Figure 26 shows a detailed structure of the SPI Module. Figure 26. SPI Module Block DiagramOpe

71AT89C51RB2/RC24180E–8051–10/06Figure 27. Full-Duplex Master-Slave InterconnectionMaster Mode The SPI operates in Master mode when the Master bit, M

72AT89C51RB2/RC24180E–8051–10/06Figure 28. Data Transmission Format (CPHA = 0)Figure 29. Data Transmission Format (CPHA = 1)Figure 30. CPHA/SS Timi

73AT89C51RB2/RC24180E–8051–10/06Error Conditions The following flags in the SPSTA signal SPI error conditions:Mode Fault (MODF) Mode Fault error in Ma

74AT89C51RB2/RC24180E–8051–10/06Figure 31. SPI Interrupt Requests GenerationRegistersThere are three registers in the Module that provide control, st

75AT89C51RB2/RC24180E–8051–10/06Reset Value = 0001 0100bNot bit addressableSerial Peripheral Status Register (SPSTA)The Serial Peripheral Status Regis

76AT89C51RB2/RC24180E–8051–10/06Reset Value = 00X0 XXXXbNot Bit addressableSerial Peripheral DATa Register (SPDAT)The Serial Peripheral Data Register

77AT89C51RB2/RC24180E–8051–10/06Hardware Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be sub-jected to softw

78AT89C51RB2/RC24180E–8051–10/06Table 60. WDTPRG RegisterWDTPRG - Watchdog Timer Out Register (0A7h)Reset Value = XXXX X000WDT During Power-down and

79AT89C51RB2/RC24180E–8051–10/06ONCE™ Mode (ON Chip Emulation)The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2without r

8AT89C51RB2/RC24180E–8051–10/06Table 11 shows all SFRs with their address and their reset value. Table 11. SFR MappingBitaddressable Non Bit addressa

80AT89C51RB2/RC24180E–8051–10/06Power Management Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle modeand the Power-down mode

81AT89C51RB2/RC24180E–8051–10/06Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)Note: These values assume VDD starts from 0V

82AT89C51RB2/RC24180E–8051–10/06Reset Recommendation to Prevent Flash CorruptionAn example of bad initialization situation may occur in an instance wh

83AT89C51RB2/RC24180E–8051–10/06be the one following the instruction that puts the AT89C51RB2/RC2 into Power-downmode. Figure 34. Power-down Exit Wav

84AT89C51RB2/RC24180E–8051–10/06Power-off Flag The Power-off flag allows the user to distinguish between a “cold start” reset and a“warm start” reset.

85AT89C51RB2/RC24180E–8051–10/06Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used withexternal program

86AT89C51RB2/RC24180E–8051–10/06Flash EEPROM MemoryThe Flash memory increases EPROM and ROM functionality with in-circuit electricalerasure and progra

87AT89C51RB2/RC24180E–8051–10/06Flash Registers and Memory MapThe AT89C51RB2/RC2 Flash memory uses several registers for its management:• Hardware reg

88AT89C51RB2/RC24180E–8051–10/06Table 66. Program Lock BitsNote: U: unprogrammed or "one" level. P: programmed or "zero" level.

89AT89C51RB2/RC24180E–8051–10/06Table 67. Default ValuesAfter programming the part by ISP, the BSB must be cleared (00h) in order to allow theapplic

9AT89C51RB2/RC24180E–8051–10/06Pin ConfigurationsFigure 2. Pin ConfigurationsP1.7CEX4/MOSI P1.4/CEX1RSTP3.0/RxDP3.1/TxD P1.3CEX0 1 P1.5/CEX2/MISOP1.

90AT89C51RB2/RC24180E–8051–10/06Table 69. Program Lock Bits of the SSBNote: U: unprogrammed or "one" level. P: programmed or "zero&

91AT89C51RB2/RC24180E–8051–10/06Bootloader ArchitectureIntroduction The bootloader manages a communication according to a specific defined protocol to

92AT89C51RB2/RC24180E–8051–10/06Functional DescriptionFigure 37. Bootloader Functional DescriptionOn the above diagram, the on-chip bootloader proces

93AT89C51RB2/RC24180E–8051–10/06Bootloader FunctionalityIntroductionThe bootloader can be activated by two means: Hardware conditions or regular bootp

94AT89C51RB2/RC24180E–8051–10/06Boot ProcessFigure 39. Bootloader processRESETHardwareCondition?BLJB!= 0?USER APPLICATIONHardwareSoftwareFCON = 00hFC

95AT89C51RB2/RC24180E–8051–10/06ISP Protocol DescriptionPhysical Layer The UART used to transmit information has the following configuration:• Charact

96AT89C51RB2/RC24180E–8051–10/06Functional DescriptionSoftware Security Bits (SSB) The SSB protects any Flash access from ISP command.The command &quo

97AT89C51RB2/RC24180E–8051–10/06Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) andsets some

98AT89C51RB2/RC24180E–8051–10/06Autobaud Performances The ISP feature allows a wide range of baud rates in the user application. It is alsoadaptable t

99AT89C51RB2/RC24180E–8051–10/06Figure 41. Command FlowWrite/Program Commands This flow is common to the following frames:• Flash/EEPROM Programming