Atmel AT85DVK-07 Spécifications télécharger pdf (Page 202)

202

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 0000 0010b

Table 221. MMCON0 Register

MMCON0 (1.B1h) – MMC Control Register 0

7 6 5 4 3 2 1 0

- DPTRR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS

Bit

Number

Bit

Mnemonic

Description

7 -

Reserved

The value read from this bit is always 0. do not set this bit

6 DPTRR

Data Pointer Reset Bit

Set to reset the read and write pointer of the data FIFO.

Cleared by hardware after pointer reset is achieved.

5 CRPTR

Command Receive Pointer Reset Bit

Set to reset the read pointer of the receive command FIFO.

Cleared by hardware after pointer reset is achieved.

4 CTPTR

Command Transmit Pointer Reset Bit

Set to reset the write pointer of the transmit command FIFO.

Cleared by hardware after pointer reset is achieved.

3 MBLOCK

Multi-block Enable Bit

Set to select multi-block data format.

Clear to select single block data format.

2 DFMT

Data Format Bit

Set to select the block-oriented data format.

Clear to select the stream data format.

1 RFMT

Response Format Bit

Set to select the 48-bit response format.

Clear to select the 136-bit response format.

0 CRCDIS

CRC7 Disable Bit

Set to disable the CRC7 computation when receiving a response.

Clear to enable the CRC7 computation when receiving a response.

Table 222. MMCON1 Register

MMCON1 (1.B2h) – MMC Control Register 1

7 6 5 4 3 2 1 0

BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN

Bit

Number

Bit

Mnemonic

Description

7-4 BLEN11:8

Block Length Bits

Refer to Ta bl e 220 for bits description.

3 DATDIR

Data Direction Bit

Set to select data transfer from host to card (write mode).

Clear to select data transfer from card to host (read mode).

1 2 ... 197 198 199 200 201 202 203 204 205 206 207 ... 262 263

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Atmel AT85DVK-07 Spécifications Page 202

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