Atmel AT85DVK-07 Spécifications télécharger pdf (Page 34)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 32. CKEN Register

CKEN (0.B9h) – Clock Enable Register

7 6 5 4 3 2 1 0

CKGENE PLLEN - PLOCK MMCKEN - SIOCKEN DNFCKEN

Bit

Number

Bit

Mnemonic

Description

7 CKGENE

Clock Generator Enable Bit

Set to enable the clock generator.

Clear to disable the clock generators.

6 PLLEN

PLL Enable Bit

Set to enable the 480 MHz PLL.

Clear to disable the 480 MHz PLL.

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

4 PLOCK

PLL Lock Flag

Set by hardware when the PLL is locked.

Cleared by hardware when the PLL is not locked.

3 MMCKEN

MMC Controller Clock Enable Bit

Set to enable the MMC controller Clock.

Clear to disable the MMC controller Clock.

2 -

Reserved

The value read from this bit is always 0. Do not set this bit.

1 SIOCKEN

SIO Controller Clock Enable Bit

Set to enable the SIO Clock.

Clear to disable the SIO Clock.

0 DNFCKEN

DF Controller / NF Controller Clock Enable Bit

Set to enable the DFC/NFC Clock.

Clear to disable the DFC/NFC Clock.

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 262 263

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Atmel AT85DVK-07 Spécifications Page 34